Nexperia 74HC373D,652
Images are for reference only.
See Product Specifications.
See Product Specifications.
Stock Code
023913
023913
Manufacturer / Brand
Nexperia
Part Number
74HC373D,652
74HC373D,652
Categories
Unit Price
$0.4350
$0.4350
Factory Lead-Time
19 Weeks
19 Weeks
Short Description
Octal transparent latch with 3-state output
Octal transparent latch with 3-state output
Datasheet
In Stock: 12766
| Qty | Unit Price | Total Price | Discount |
|---|---|---|---|
| 1 | $0.4350 | $0.4350 | |
| 10 | $0.3680 | $3.6800 | -15.4% |
| 100 | $0.2910 | $29.1000 | -33.1% |
| 250 | $0.2700 | $67.5000 | -37.93% |
| 500 | $0.2310 | $115.5000 | -46.9% |
| 1000 | $0.1850 | $185.0000 | -57.47% |
| 2000 | $0.1660 | $332.0000 | -61.84% |
| 4000 | $0.1570 | $628.0000 | -63.91% |
| 10000 | $0.1510 | $1,510.0000 | -65.29% |
Description
The Nexperia 74HC373D,652 is an octal transparent latch with three-state outputs. This device operates with the voltage range of 2 to 6 volts, and it is suitable for interfacing with TTL, CMOS, and PMOS logic levels. This latch is designed with a high output drive capability, which makes it ideal for driving highly capacitive loads. The device comes in an SOIC-20 package, which is suitable for surface mount applications.
This Nexperia 74HC373D,652 latch features an input enable pin that allows the device to operate as a transparent latch. When the input enable pin is low, the device holds the data state at the input. When the input enable is high, the device transfers the data state to the output. This device has eight latches with three-state outputs, which makes it suitable for storage of data in address and data busses. Additionally, this device has a latch-enable input, which allows for the storage of data independently of the three-state outputs. The device has a symmetrical output impedance and a balanced propagation delay. Thus, it is suitable for applications requiring a fast transition time and low power consumption
This Nexperia 74HC373D,652 latch features an input enable pin that allows the device to operate as a transparent latch. When the input enable pin is low, the device holds the data state at the input. When the input enable is high, the device transfers the data state to the output. This device has eight latches with three-state outputs, which makes it suitable for storage of data in address and data busses. Additionally, this device has a latch-enable input, which allows for the storage of data independently of the three-state outputs. The device has a symmetrical output impedance and a balanced propagation delay. Thus, it is suitable for applications requiring a fast transition time and low power consumption
Product Attributes
| Circuit | 8:8 |
| Current - Output High, Low | 7.8mA, 7.8mA |
| Delay Time - Propagation | 12ns |
| Independent Circuits | 1 |
| Logic Type | D-Type Transparent Latch |
| Mounting Type | Surface Mount |
| Operating Temperature | -40°C ~ 125°C |
| Output Type | Tri-State |
| Package / Case | 20-SOIC (0.295", 7.50mm Width) |
| Packaging | Tube |
| Part Status | Obsolete |
| Supplier Device Package | 20-SO |
| Voltage - Supply | 2V ~ 6V |
